Ultra dense trench-gated power device with the reduced drain-source feedback capacitance and Miller charge

ABSTRACT

The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. Covering the wells is an upper source layer of the first conductivity type that is heavily doped. The trench structure includes a sidewall oxide or other suitable insulating material that covers the sidewalls of the trench. The bottom of the trench is filled with a doped polysilicon shield. An interlevel dielectric such as silicon nitride covers the shield. The gate region is formed by another layer of doped polysilicon. A second interlevel dielectric, typically borophosphosilicate glass (BPSG) covers the gate. In operation, current flows vertically between the source and the drain through a channel in the well when a suitable voltage is applied to the gate.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.11/178,215 filed Jul. 8, 20005 which claims the benefit of U.S.Provisional Patent Application Ser. No. 60/274,760, filed Mar. 9, 2001(expired), U.S. patent application Ser. No. 10/092,692 filed Mar. 7,2002, now U.S. Pat. No. 6,683,346 and U.S. patent application Ser. No.10/678,444 filed Oct. 1, 2003, now U.S. Pat. No. 6,929,988.

FIELD OF THE INVENTION

The present invention is directed to semiconductor devices and, moreparticularly, to a trench MOSFET with reduced Miller capacitance havingimproved switching speed characteristics.

BACKGROUND OF THE INVENTION

The semiconductor industry is witnessing an increasing demand forlow-output-voltage DC-DC converters with very fast transient responseand higher power efficiency for high frequency power conversionapplications. When the operation frequency reaches 1 MHz or even higher,the power losses of a synchronous buck DC-DC converter will be dominatedby the switching losses. Switching losses in a power MOSFET occur duringcharging/discharging the drain-gate feedback capacitance. Thecorresponding gate charge is called Miller Charge. Thus, the reductionof Miller capacitance is one of most important focus to improve DC-DCconverter efficiency.

Also, as the cell density and speed of a microprocessor increases, morecurrent is needed to power the microprocessor. This means that the DC-DCconverter is required to provide a higher output current. The increaseof the output current raises the conduction loss of not only the lowerswitches but also the upper switches in synchronous DC-DC converter.Therefore, in order to power an advanced microprocessor, the powerMOSFETS, which are used as the upper and the lower switches in a DC-DCconverter must have both low switching power losses and low conductionpower losses. The switching losses can be reduced by loweringon-resistance. Unfortunately, lowering the on-resistance raises theMiller capacitance. For example, in order to reduce the on-resistance ofa power MOSFET, the most efficient way is to reduce the device cellpitch and increase the total channel width. Both of these result in anincrease of the drain-gate overlay area. As the consequence, thedevice's Miller capacitance, or Miller charge increases.

Due to gate to drain capacitance's significant impact on deviceswitching speed, a series of improvements for minimizing it's impacthave been proposed. These improvements include tailoring of source-drainion implant angles and gate spacers, in order to obtain sufficient gateoverlap of source-drains for maintaining low channel resistance, whilestill minimizing the associated capacitance values. One such effort tominimize Miller capacitance is a process step that locally increases thegate oxide thickness in the region of gate to drain overlap. However,that process is difficult to control because you need to maintainoverlap while growing the thick oxide in the bottom of the trench andetching back. Therefore, what is needed is a method that will achievelow switching power losses and low conductivity power losses.

SUMMARY OF THE INVENTION

The present invention is directed towards a power device that has lowswitching power losses and low conductivity power losses. A power devicehaving features of the present invention comprises a first substratelayer that is highly doped with a dopant of a first conductivity type,forming a drain. Over this first layer is a second layer that is lightlydoped with the same conductivity dopant as the first layer. Above thissecond layer is a third layer, doped with a second conductivity dopantthat is opposite in polarity to the first conductivity type. A fourthlayer highly doped with the first conductivity dopant, is on theopposite surface of the semiconductor substrate. A trench extends fromthis fourth layer, into the second layer. This trench divides the fourthlayer into a plurality of source regions. The trench also has sidewallsadjacent to the third and fourth layers for controlling a channel layer.Finally, this trench also has upper and lower conductive layers that areseparated by a dielectric layer.

According to another aspect of the invention, the upper conductive layerin the trench forms a gate electrode for controlling current through achannel adjacent the sidewall of the trench. The polysilicon gate layer,the polysilicon shield layer and the interlevel dielectric layer aresuitably sized so that the bottom of the polysilicon gate layer isproximate the curvature of the well region. This will minimize theoverlap between the gate and drain, and therefore minimize thegate-to-drain capacitance.

According to still another aspect of the invention, the deviceoriginally described can have a source metal layer over the device andin electrical contact with the fourth layer, so that it is in contactwith the source regions. This source metal also is in contact with thethird layer doped with the second conductivity type. This metal layerwill also be in contact with the lower conductive layer of the trench atperipheral locations around the cells of the device. The lowerconductive layer, or shield layer, will be at the same electrostaticpotential as the source. Now the capacitance at the bottom of the trenchis no longer gate-to-drain it is now gate-to-source, because the shieldis tied to the source.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-section of a DMOS cell structure.

FIG. 1A is a table showing comparative results.

FIG. 2 is a first graph showing gate voltage as a function of gatecharge for new and conventional 0.2 micron cell pitch devices.

FIG. 3 is a second graph similar to FIG. 2 for 0.3 micron cell pitchdevices.

FIG. 4 is an n-type doped epi-layer grown on the N+ substrate.

FIG. 5 is pad oxidation followed by the Boron implant and annealing.

FIG. 6 is LTO oxide deposition, followed by the LTO pattern definitionby using photo-mask/etch steps.

FIG. 7 is silicon etch to form the trench structure.

FIG. 8. is LTO removal followed by Sacrificial Oxidation and Gateoxidation.

FIG. 9 is polysilicon fill.

FIG. 10 is polysilicon recess etch forming the polysilicon shield layer.

FIG. 11 is IDL (SiN) deposition;

FIG. 12 is IDL (SiN) recess etch.

FIG. 13 is polysilicon refill.

FIG. 14 is polysilicon recess etch forming the polysilicon gate.

FIG. 15 is IDL (BPSG) deposition.

FIG. 16 is IDL (BPSG) etch back and planarization.

FIG. 17 is boron/phosphorous implant and drive to form the P+ body/N+source.

FIG. 18 is BOE dip, followed by Ti/TiN barrier layer formation and Metaldeposition (SiAl).

FIG. 19 is a section taken through the center of the trench of FIG. 18.

DETAILED DESCRIPTION OF THE DRAWINGS

The new device structure is shown in FIG. 1. This new device 10 includesa buried polysilicon shield layer 38 between the polysilicon gate 34 andthe drain terminal 12. The polysilicon shield layer 38 contacts thesource metal 20 at periphery of the die, and has the same electrostaticpotential as the Source Metal 20. See FIG. 19. As the consequence, thegate and drain displacement currents flow through the source 18 and thepolysilicon shield 38 during the switching transient, and the feedbackbetween the drain terminal and the gate terminal during the gate turnon/off transients is greatly suppressed. Making use of this new devicestructure, a much lower Miller Charge can be obtained with minimumsacrifice of the on-resistance. Furthermore, the contradiction betweenthe on-resistance and Miller Charge can be depressed significantly. Theelectrical characteristics of both the new device and the conventionaltrench-gated power MOSFET were evaluated by using the computersimulations. The results are summarized in FIG. 1A. The new device 10disclosed in this invention has much less Miller capacitance, Cgd, witha small increase of the on-resistance when compared to the conventionaldevice without a shield. For example, for the device with cell pitch 2.0μm, the new device achieves about 84% reduction of gate-to-draincapacitance (Cgd) with only 18% increase of the on-resistance per unitarea, RSP, when compared to the conventional device. The figure ofmerit, RSP*Cgd, is defined as the product of on-resistance and Millercapacitance. Results show about 80% improvement when comparing the newdevice to the conventional device. The gate voltage vs. gate chargecharacteristics of both devices are given in FIGS. 2 and 3, respectivelyfor 2.0 μm cell pitch and 3.0 μm cell pitch. These figures demonstratethat the new device disclosed in this invention has dramatically reducedthe Miller charge, which is represented by the width of plateau portionin the curves of the gate voltage vs. gate charge. Additionally, becauseof the reduction in gate-to-drain capacitance, the device can be madevery dense without sacrificing switching speed.

FIG. 1 is a cross-sectional view of a single cell of a multi-cellulartrench gate device 10 of the present invention. Those skilled in the artwill understand that the trench gate device 10 may be used in connectionwith power devices such as DMOS devices as well as other power devices,including insulated gate bipolar transistors (IGBTs) and MOS gatedthyristors. In such devices the cellular pattern shown in FIG. 1 isrepeated by having multiple cells, all of which are divided by thetrench gate.

The cellular structure of a typical MOSFET 10 includes a substrate 12that has a highly doped drain or N+ region. Over the substrate 12 thereis a more lightly doped epitaxial layer 14 of the same doping polarity.Above the epitaxial layer 14 is a well region 16 formed of opposite orP-type doping. Covering the P-wells 16 is an upper source layer 18 thatis heavily N-type doped. The trench structure 30 includes a sidewalloxide 32 or other suitable insulating material that covers the sidewallsof the trench 30. The bottom of the trench 30 is filled with apolysilicon shield 38. An interlevel dielectric such as silicon nitride36 covers the shield 38. The gate 34 is formed by another layer ofhighly doped polysilicon. A second interlevel dielectric 33, typicallyborophosphosilicate glass (BPSG) covers the gate 34. In operation,current flows vertically between the source 18 and the drain 12 througha channel in the well 16 when a suitable voltage is applied to the gate34.

The device 10 is formed by the series of process steps shown in FIGS.4-17. Initially, a suitable substrate 8 is highly doped to form an N+region 12. Then, an epitaxial layer 14 is grown on the other surface ofthe substrate 8. The epitaxial layer 14 is either grown as a lightlydoped N− layer or is then suitably doped as N− after it is grown. Pleasenote that although the epitaxial layer 14 is shown larger than thesubstrate, the difference in size is strictly for purposes of explainingthe invention. Those skilled in the art understand that the substrate isnormally significantly greater in thickness than is the epitaxial layer.

FIG. 5 shows boron ions 40 implanted into the upper surface of theepitaxial layer 14 to form a latent P-well 16 in FIG. 6. FIG. 6 alsoshows the surface of the epitaxial layer covered with a low-temperatureoxide 42 that is patterned to expose future trench regions. Trenches areetched as shown in FIG. 7. Turning to FIG. 8, the trenches 30 may beetched by any suitable process, including a wet etch or a dry plasmetch. Such etching is conventional and is known to those skilled in theart. After completion of the etching, the entire wafer is subjected toan oxidation process in order to grow a relatively thin gate oxide layer32 over the entire wafer, including the sidewalls of the trench 30.Prior to growing the gate oxide layer, the low-temperature oxide mask isstripped. The oxidation step is performed at a temperature high enoughto drive in the boron implants and form well region 16.

In a next step, shown in FIG. 9, the entire wafer is covered with apolysilicon layer 38 that fills the trench 30. The polysilicon layer 38is etched away until it leaves a residual polysilicon shield 38 in thebottom of the trenches 30, as shown in FIG. 10. Turning now to FIG. 11,an interlevel dielectric layer 36 is formed from silicon nitride orother suitable insulator over the entire wafer, including in thetrenches 30. The interlevel dielectric layer 36 is suitably etched, asshown in FIG. 12, to leave a layer within the trenches and covering thepolysilicon shield layer 38. Next, FIG. 13 shows a polysilicon gatelayer 34 deposited over the entire wafer and into the trenches 30. Thepolysilicon gate includes highly doped polysilicon so as to provide aconductive gate material. Other materials are possible, but polysiliconis the preferred material. The polysilicon gate layer and thepolysilicon shield layer 38 and the interlevel dielectric layer 36 aresuitably sized so that the bottom of the polysilicon gate layer 34 isproximate the curvature of the well region 16. This will minimize theoverlap between the gate and drain, and therefore minimize thegate-to-drain capacitance.

Turning to FIG. 14, the polysilicon gate layer 34 is etched in order toprovide room in the trench for an interlevel dielectric layer. Asuitable IDL layer 33, as shown in FIG. 15, comprising BPSG is depositedover the entire wafer 10 and into the remainder of the trenches. TheBPSG layer 33 is planarized, as shown in FIG. 16, to approximately thesame level as the top of the epitaxial layer 14. The entire surface ofthe device is subjected to a suitable N+ source implant such asphosphorous or arsenic. The source implant is suitably driven into anappropriate depth in order to form the source regions 18 as shown inFIG. 17. The wafer is then covered with a layer of metal 20 that formsthe source metal which is then suitably patterned and finished to createthe device. A section 19-19′ is taken through the center of the trenchof FIG. 18. A portion of the resulting profile at the edge of the waferis shown in FIG. 19. The polysilicon shield 38 is in electrical andmechanical contact with the source 20 at the die periphery. As a result,the polysilicon shield layer 38 is electrically shorted to the sourcemetal 20. This source metal is also in contact with the third layer.(not shown)

The remaining process steps are standard backend process steps for powersemiconductor devices, including top surface tape, wafer grind, removalof tape and backside metalization, etc. While this invention has beendescribed as having a preferred design, the present invention can befurther modified within the spirit and scope of this disclosure. Thisapplication is therefore intended to cover any variations, uses, oradaptations of the present invention using the general principlesdisclosed herein. Furthermore, this application is intended to coversuch departures from the present disclosure as come within the known orcustomary practice in the art to which this invention pertains and whichfall within the limits of the appended claims.

1. A semiconductor device having improved and reduced Miller capacitance in a repeated cellular structure, wherein the cells of the device comprise: a substrate having one surface with a first layer highly doped with a first conductivity dopant and forming a drain; a second layer over the first layer and lightly doped with a first conductivity dopant; a third layer over the second layer and doped with a second conductivity dopant opposite in polarity to the first conductivity component, and forming a PN junction with the second layer; a fourth layer on the opposite surface of the semiconductor substrate and highly doped with a first conductivity dopant; a trench structure extending from the fourth layer into the substrate and dividing the fourth layer into a plurality of source regions, said trench having spaced apart sidewalls and a floor with an insulating layer on the sidewalls and floor, upper and lower conductive layers separated by a dielectric layer; and a source metal layer over the device and in electrical contact with the fourth layer to contact the source regions and in electrical contact with the lower conductive layer of the trenches at peripheral locations around the cells of the device.
 2. The semiconductor device of claim 1 wherein the length of the upper conductive layer is greater than the length of the lower conductive layer.
 3. The semiconductor device of claim 1 wherein the width of the trench is less than the depth of the trench.
 4. The semiconductor device of claim 1 wherein top of the upper conductive layer in the trench is proximate the bottom of the fourth highly doped layer.
 5. The semiconductor device of claim 1 wherein a floor portion of the trench is disposed below the lower level of the third layer and said floor portion is rounded to reduce the concentration of electromagnetic field at the bottom of the trench.
 6. The semiconductor device of claim 1 wherein the conductive layers in the trench comprise doped polysilicon.
 7. The semiconductor device of claim 1 wherein the dielectric layer separating the two conductive layers is silicon nitride.
 8. The semiconductor device of claim 1 wherein the upper conductive layer in the trench forms a gate electrode for controlling current through a channel adjacent the sidewall of the trench.
 9. The semiconductor device of claim 1 wherein the second layer comprises a layer of dopant that curves upwardly toward the surface of the substrate proximate the sidewalls of the trench and the bottom of the upper layer of the trench conductor is at about the same level as the PN junction proximate the sidewall of the trench.
 10. The semiconductor device of claim 1 wherein the top of the lower conductive layer is below the bottom of the third layer of second conductivity.
 11. The semiconductor device of claim 1 wherein said upper and lower conducting layers have approximately the same width in their respective regions adjacent the dielectric layer separating them.
 12. The semiconductor device of claim 11 wherein the source metal is in contact with the third layer of the second conductivity type.
 13. The semiconductor device of claim 1 further comprising a second interlevel dielectric layer above said upper conductive layer.
 14. The semiconductor device of claim 13 wherein said second interlevel dielectric layer is borophosphosilicate glass.
 15. The semiconductor device of claim 1 wherein the sidewalls and floor of said trench include an oxide layer.
 16. The semiconductor device of claim 1 wherein the first dopant is p-type and the second dopant is n-type.
 17. The semiconductor device of claim 1 wherein the first dopant is n-type and the second dopant is p-type. 